Branch Delay Slot — In der Rechnerarchitektur ist eine Branch Delay Instruction ein Maschinenbefehl, der direkt einem bedingtem Verzweigungsbefehl folgt und unabhängig davon, ob die Verzweigung genommen wurde oder nicht, immer ausgeführt wird. Die Position eines… … Deutsch Wikipedia
Delay slot — In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or… … Wikipedia
Branch predictor — In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. This is called branch prediction. Branch predictors are… … Wikipedia
Branch (computer science) — For other uses, see Branch (disambiguation). A branch is sequence of code in a computer program which is conditionally executed depending on whether the flow of control is altered or not (at the branching point). The term can be used when… … Wikipedia
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… … Wikipedia
Reduced instruction set computer — The acronym RISC (pronounced risk ), for reduced instruction set computing, represents a CPU design strategy emphasizing the insight that simplified instructions which do less may still provide for higher performance if this simplicity can be… … Wikipedia
Explicitly parallel instruction computing — (EPIC) is a term coined in 1997 by the HP Intel alliance [cite web url = http://www.hpl.hp.com/techreports/1999/HPL 1999 111.pdf title = EPIC: An Architecture for Instruction Level Parallel Processors accessdate = 2008 05 08 last = Schlansker and … Wikipedia
Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… … Wikipedia
Hazard (computer architecture) — Hazards are problems with the instruction pipeline in central processing unit (CPU) microarchitectures that potentially result in incorrect computation. There are typically three types of hazards: data hazards structural hazards control hazards… … Wikipedia
